So PCIe is a packet network faking the traditional PCI bus. To make a long story short, the PCIe standard goes a long way to look like good old PCI to an operation system unaware of PCIe. There are still Vendor/Product IDs, and several mechanisms to mimic old behavior. There’s still the plug-and-play configuration done, and the cards are accessed in terms of reads and writes to address and I/O space, just like before. Even though it’s a packet-based network, it’s all about addresses, reads, writes an interrupt. On the other hand, the PCIe standard was deliberately made to behave very much like classic PCI.
#SOFTWARE LIKE EXPRESS TALK MAC#
There are no MAC addresses, but we have the card’s physical (“geographic”) position instead to define it, before it’s allocated with high-level means of addressing it (a chunk in the I/O and address space).Īs a matter of fact, a minimal (1x) PCIe connection merely consists of four wires for data transmission (two differential pairs in each direction) and another pair of wires to supply the card with a reference clock. The similarity goes further: The communication takes the form of packets transmitted over these dedicated lines, with flow control, error detection and retransmissions. Exactly like a local Ethernet network, each card has its own physical connection to the switch fabric.
PCIe is more like a network, with each card connected to a network switch through a dedicated set of wires. The previous PCI versions, PCI-X included, are true buses: There are parallel rails of copper physically reaching several slots for peripheral cards. The first thing to realize about PCI express (PCIe henceforth), is that it’s not PCI-X, or any other PCI version. I also suggest to read about PCI configuration, in particular the part about enumeration. For an overview of these, I suggest Wikipedia’s entry on this. I’ve also published a sample TLP sniff dump of a session, which may help understand how the machinery works.Īnd I rely on other sources to describe form factors, lane counts, data rates and such. All I’m trying to do here is to making it more human readable. The name of the game if to get the details right, so that the device works properly in environments that are not at hand for testing.ĭon’t pick on me for not describing the whole picture, or using inaccurate definitions. There is no substitute to reading the original spec, though.
This is based upon the official PCI Express specification 1.1, but applies very well to later versions. So once I made the effort to figure that out for myself, I decided to write this little guide, which will hopefully help others get a softer start. While I was writing the Xillybus IP core for PCI express, I quickly found out that it’s very difficult to start off: Online resources as well as the official spec bombards you with gory details about the nuts and bolts, but says much less about what the machine is supposed to do.
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